The trend in CMOS-based processing technology is to produce integrated circuit (IC) cores having a higher density of transistors and faster clock rates than their predecessors. I/O signals, which electrically connect the IC core to external components in the discrete environment, are accessed through I/O circuit pads that surround the IC core. The IC core and the I/O circuit pads are generally fabricated from the same processing technology. The performance of the IC core is improved by shrinking the feature sizes of the devices, such as field-effect transistors (FETs). Unfortunately, reducing the feature sizes proportionally decreases the maximum operating voltage that the FETs can withstand. For example, an I/O circuit pad, fabricated from a CMOS process having 0.5 micron features, withstands a maximum operating voltage of .about.3.6 volts. The maximum operating voltage of the I/O circuit pad is insufficient to drive the external components which have a higher voltage requirement, typically 5 volts. Furthermore, if the IC is driven at greater than the maximum operating voltage, the IC will fail.
One attempt to resolve the mismatched voltage requirements is to increase the robustness of the fabrication process by increasing the thickness of the gate-oxide layer. A thick gate-oxide layer provides each and every FET ability to support the higher voltage requirement. However, this robustness decreases the performance of the IC because the overall gain of the IC is reduced. Reducing the gain minimizes the beneficial reasons which occur by reducing the feature size.
Other attempts have included increasing the complexity of the CMOS fabrication process so there are two sets of devices where each set meet different voltage requirements. Each set of devices requires a different gate-oxide and a different polysilicon deposition. Each additional deposition requires a separate mask. The resulting hybrid process increases the manufacturing costs of the IC.
One way to avoid the aforementioned processing-based solutions is to use a "level-shift" chip as an external component. The IC core and the I/O circuit pads are fabricated from the same process. The "level-shift chip" is fabricated from a process that supports the discrete voltage requirement by stepping up the core output signals to support the discrete voltage range and stepping down the external drive signals to support the IC core voltage range. This chip is a waste of much needed space on the printed circuit board and degrades performance.
An I/O circuit that transforms voltages between different voltage requirements without degrading the overall performance of the integrated circuit and maximizing use of space on the printed circuit board or multi-chip substrate could be beneficial. It would be a further benefit if this I/O circuit and the IC core were fabricated from the same process to minimize manufacturing costs.